FIG. 1 diagrammatically illustrates an AT&T-compatible digital carrier terminal or D4 channel bank 10, such as that manufactured by Adtran Corporation, Huntsville, Ala., through which digital communications may be provided by a digital carrier telephone network to digital signalling equipment located at a customer's premises 20. The channel bank 10 typically contains a line interface unit (LIU) 12 which interfaces one end of a T1 (1.544 Mb/s) time division multiplex (TDM) digital communications link 14. A second end of T1 TDM link 14 may be connected to another office, such as one containing an operational support system (OSS) 16, located remotely with respect to the office in which D4 channel bank 10 is installed.
Also contained in the D4 channel bank 10 is an office channel unit data port (OCU-DP) 18, which is coupled to LIU 12 via an intra D4 bank PCM communications link 15. OCU-DP 18 is configured to support a plurality of (e.g. twenty-four) channel units, which may be either analog channel units (analog cards) that source pulse code modulated analog (voice) signals, or digital channel units (digital cards) that source digital data, with each card being associated with a respective (64 Kb/s) time slot Ti of the T1 TDM link 14. (In accordance with industry standard card slot assignment identification, a respective card slot is identified by an associated time slot.) OCU-DP 18 is operative to interface bipolar signals on respective portions 21T and 21R of a local four-wire DS0 metallic (copper) link 21, which is coupled to a digital data service termination (DDST) 22, terminating the metallic loop 21 with a data service unit/channel service unit (CSU/DSU) 23 located at the customer's premises 20.
The LIU 12 and OCU-DP 18 within the D4 channel bank 10 include respective transmit/receive buffers associated with the respective ports of a respective channel unit. These buffers are controlled by a supervisory microcontroller for interfacing DS1-formatted data traffic from the T1 link side of the terminal, retiming the traffic as a bipolar data stream for transmission as a DS0 (bipolar) data stream or analog signals from the D4 channel bank 10 to the customer's site 20, and reconverting signals, supplied from the customer site 20 to OCU data port 18, into DS1 data frames for transmission over T1 link 14 to the remote site.
The component and bus architecture through which LIU 12 and OCU-DP 18 of D4 channel bank 10 communicate with one another by way of PCM communications link 15 is diagrammatically shown FIG. 2. As shown therein, a respective channel unit 19 has a transmitter section 31 and a receiver section 33. In the case of a digital channel unit, DS0 data from the four wire metallic loop 21 is supplied from the customer site termination equipment. In the case of an analog card, the transmit section 31 is coupled to receive incoming analog (voice) signals. Similarly, for a digital channel unit, receiver section 33 couples DS0 data to four wire metallic loop 21 for delivery to the customer site termination equipment. For an analog card the receiver section 33 supplies analog signals to the local loop.
To provide for intrabank communications between a channel unit 19 and the line interface unit 12, respective transmit and receive units 35 and 34 are employed. To accommodate installation of a digital card in a respective the backplane card/time slot, a set of transmission links 40 couple transmit section 31 to a transmit unit 35. Transmission links 40 include an ATDATA bus 44 and a DTDATA bus 45. ATDATA bus 44 is employed to transport encoded PAM signals from an analog channel unit to transmit unit 35, while DTDATA bus 45 is employed to transport serialized digital data bits from a digital channel unit to transmit unit 35, during a respective time slot Ti assigned to that channel unit.
Transmission links 40 further include a set of transmit sequence control leads 41 on which transmission control signals TX.sub.-- CNTL signals from transmit unit 35 are asserted for controlling the format of data transmissions from the channel unit. Link 42 is a clock lead on which a transmit clock signal TD-CLK is asserted by transmitter section 31. In response to the control and clock signals on links 41 and 42, the transmitter section 31 of a digital channel unit decodes its respective channel select strobe and transmits data packets onto transmit data DTDATA bus 45 in a respective one of a plurality (e.g. 24) multiplexed channel unit time slots of a multi-channel (e.g. 24 channel) unit digroup within the D4 bank.
Pursuant to industry (AT&T-defined) communication standards, the channel select strobe occurs at an 8 KHz rate, so that with an eight bit byte being asserted for each strobe, a 64 Kb/s (DS0) channel is provided for a respective DS1 line. As data is serialized out over the DTDATA bus 45, transmit unit 35 collects the 192 bits (comprised of eight bits from each of the (24) channel units), appends a framing bit, and outputs the resulting DS1-formatted (193 bit) PCM data stream onto a TPCM link 51, and an associated transmit clock signal via TCLK link 53 to the LIU 12. The line interface unit 12 couples the formatted DS1 data onto the digital T1 carrier for transmission over link 14.
Transmission links 40 further include a transmit enable (TNEN) lead 43, which is coupled through a pull-up resistor 46 to a prescribed high (logical `1` state representative) voltage level V.sub.H. As a result of this pull-up resistor 46, in the absence of any card being installed in a card/time slot of interest, the TNEN lead 43 will be normally in a logical high or `1` state during that time slot. When a channel unit is installed in a respective time/card slot, it identifies itself as either a digital channel unit or an analog channel unit by establishing the logical state of the TNEN lead 43 to a logical `1` or a logical `0` during its respective time slot.
In particular, if the installed channel unit is a digital channel unit, the TNEN lead remains in its normally pulled up logical high or `1` state, described above. With the TNEN lead 43 being a logical `1`, the transmit unit 35 is instructed to pass (digital) data that has been asserted onto the DTDATA bus 45 by the digital channel unit over a PCM lead 51 to the LIU 12. On the other hand, if the installed channel unit is an analog channel unit, it asserts a low (logical `0` state representative) voltage on the TNEN during its time slot. When the transmit unit reads the logical state of the TNEN lead 43 as a logical `0`, it infers that the channel unit for the time slot of interest is an analog channel unit, and proceeds to encode the analog state of the ATDATA bus 44 (which presumably corresponds to PAM data sourced from an analog channel unit of interest) into PCM format, and assert that encoded data over the PCM lead 51 to the LIU 12.
On the DS1 receive side, incoming T1 carrier signals from link 14 are received by line interface unit 12, and extended superframe format is converted into superframe formatted signals, as necessary. Payload or signalling bits are not altered. The DS1 data is asserted onto a receive RNPCM bus 61, which is coupled to receive unit 34 and to the receiver section 33 of each channel unit of the D4 channel bank. The DS1 clock within the T1 data is recovered by LIU 12 and applied as a recovered clock signal on RCLK link 63, which is also coupled to receive unit 34 and to the receiver section 33 of each channel unit 19.
The receive unit 34 synchronizes its timing with the DS1 framing pattern of the received signal and supplies channel unit control signals over RX.sub.-- CNTL link 65 to the receiver section 33 of each channel unit in the D4 bank. This allows each channel unit to decode its channel select strobe for the received data and to extract its signals from the associated time slot of RNPCM data bus 61. In the case of an analog channel unit, the received PCM data is converted into analog format for delivery to the customer's analog equipment.
As pointed out above, in order to determine whether a channel unit installed in a respective card/time slot of the channel bank is a digital channel unit or an analog channel unit, the transmit unit 35 reads the state of the TNEN lead 43. Since the default (logical `1` ) state of the TNEN lead 43 is not changed by the installation of a digital channel unit, the transmit unit 35 will not assert PCM encoded PAM analog data derived from the ATDATA bus 44 onto the PCM lead 51, unless the TNEN lead 43 is in a logical `0` state.
Now although the intended operation of analog channel unit is to actively pull the TNEN lead low only during its associated time slot, it also does so upon power-up, when first installed into its card slot. Indeed, in the course of `booting up` after being inserted into the channel bank, the analog card is prone to assert a logical low condition on the TNEN lead for a period of time that overlaps or `bleeds` into one or more time slots of other channel units. As a result, during such time slots the logical `0` state of the TNEN lead will cause the transmit unit 35 to infer that it is to read the ATDATA bus 44, rather than the DTDATA bus 45. If the overlapped time slots during which the TNEN lead is asserted low by the newly installed analog channel unit are associated with digital channel units, the transmit unit's reading of the ATDATA bus 44 will cause the serialized digital data bits that should have been passed directly from the DTDATA bus 45 to the PCM bus 51 to be erroneously replaced with inadvertently PCM encoded spurious noise on the analog PAM lead, commonly termed `bank hits`, thereby corrupting the digital data that should have been transmitted. This causes customers with live data circuits to experience retransmission errors and sometimes request discounts from the service provider for errored seconds in the circuit.